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Catapult C Synthesis, a commercial electronic design automation product of Calypto Design Systems, is a high-level synthesis tool, sometimes called algorithmic synthesis or ESL synthesis. Catapult C takes ANSI C/C++ and SystemC inputs〔Chip Design (Bridging ESL and High-Level Synthesis )〕 and generates register transfer level (RTL) code targeted to FPGAs and ASICs.〔University of Oulu (Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA Wireless System Using C Synthesis )〕 ==History== In 2004, Mentor Graphics formally announced its Catapult C high level synthesis product offering hierarchical design support for synthesizing pipelined, multi-block subsystems from untimed ANSI C/C++ descriptions. Catapult C's main functionality was generating RTL (VHDL and Verilog) targeted to ASICs and FPGAs. Users specified constraints for timing and area, and provided a clock period and destination technology. Mentor also announced a Catapult C Library Builder for ASIC Designers to collect detailed characterization data.〔EETimes: ( High-level synthesis rollouts enable ESL )〕 In 2005, Mentor announced extensions to Catapult C to automatically create SystemC transaction-level models and wrappers, for simulation of the design in verification environments supporting SystemC. Mentor also introduced interface synthesis to map the data transfer implied by passing of C++ function arguments to hardware interfaces such as wires, registers, handshaked registers, memories, buses or more complex user-defined interfaces.〔SOCCentral ( Mentor Graphics Extends Catapult C Synthesis Product )〕 In 2006, Mentor announced Catapult SL (System Level) for automatically creating signal processing subsystems. Catapult SL could coordinate the partitioning of sequential C operations into multiple blocks within the subsystem, including partitioning into multiple clock domains. Catapult SL automatically inserts appropriate inter-block channels and memory buffers to assemble the sub-system.〔SOCCentral ( Mentor Introduces High-Level Synthesis to Create High-Performance Subsystems from Pure ANSI C++ ).〕 In January 2009, Mentor announced an integration between Catapult C and its Vista SystemC design and simulation environment to automatically generate transaction-level models (TLM). In this process, the untimed ANSI C++ input to Catapult is encapsulated in a TLM wrapper; timing information is extracted from the synthesis results and back-annotated in the resulting model. The flow is compatible with the TLM-2.0 standard from the Open SystemC Initiative (OSCI).〔EETimes (Mentor TLM 2.0 design flow )〕 In June 2009, Mentor announced that it enhanced Catapult C with the ability to synthesize control logic, create power-optimized RTL netlists, with automatic multi-level clock gating, and an automated verification flow to enable a debug of the RTL against the original C++ input.〔SCDsource ( Mentor Catapult C synthesizes control and power management )〕 In January 2010, Mentor announced the ability for Catapult C to take direct SystemC input, including both cycle-based and transaction level (TLM) support.〔Chip Design (Bridging ESL and High-Level Synthesis )〕 In May 2011, Mentor announced that Catapult C supported TLM synthesis. Abstract TLM models are converted to pin-accurate, protocol-specific, SystemC models, and from there, synthesized to RTL code. Existing synthesizable descriptions can be converted to TLMs.〔EETimes (Mentor’s TLM Synthesis links virtual prototyping and hardware implementation )〕 In August 2011, Catapult C was acquired by Calypto Design Systems.〔EETimes (Calypto acquires Mentor's Catapult C )〕 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Catapult C」の詳細全文を読む スポンサード リンク
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